A low cost soft mapper for turbo equalization with high order modulation

Author

Licai Fang ; Qinghua Guo ; Defeng Huang ; Nordholm, Sven Erik

Author_Institution

Sch. of EECE, Univ. of Western Australia, Perth, WA, Australia

fYear

2012

fDate

4-7 Nov. 2012

Firstpage

305

Lastpage

308

Abstract

In an MMSE based turbo equalization system, a soft mapper calculates the symbol mean and variance based on extrinsic Log-Likelihood-Ratios (LLRs) information coming from a Soft-Input Soft-Output (SISO) decoder. In this paper, we investigate the complexity of this module, and in particular, we employ a 3-segment linear approximation approach to calculate the mean and variance of data symbols from LLRs. For FPGA and VLSI implementation, we propose novel piecewise linear functions which map LLR to the mean and variance directly without the use of any two-variable-input multipliers. Simulation results for 16-QAM and 64-QAM show that the no multiplier approach has close BER performance to the 3-segment linear approximation approach with multipliers.

Keywords

VLSI; approximation theory; decoding; equalisers; field programmable gate arrays; least mean squares methods; multiplying circuits; quadrature amplitude modulation; turbo codes; 16-QAM; 64-QAM; BER performance; FPGA; LLR information; MMSE based turbo equalization system; SISO decoder; VLSI; data symbol mean; data symbol variance; extrinsic log-likelihood-ratio information; high order modulation; low cost soft mapper module; piecewise linear functions; soft-input soft-output decoder; three-segment linear approximation approach; two-variable-input multipliers; Bit error rate; Decoding; Educational institutions; Equations; Linear approximation; Mathematical model; Modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2012 International

Conference_Location

Jeju Island

Print_ISBN

978-1-4673-2989-7

Electronic_ISBN

978-1-4673-2988-0

Type

conf

DOI

10.1109/ISOCC.2012.6407101

Filename

6407101