High-throughput turbo decoder design with new interconnection network for LTE/LTE-A system

In this paper, we design and implement a high-throughput turbo decoder for the 3^rd Generation Partnership Project (3GPP) Long Term Evolution-Advanced (LTE-advanced) system. To support the high data rate, we adopts eight radix-4 parallel soft-in/soft-output decoders. The properties of quadratic permutation polynomial (QPP) interleaver are exploited, and a new interconnection network is designed with simple rotator and control logic. The storages and arithmetic units related with branch metric are saved by taking advantage of the odd symmetry of all the possible combinations. A re-timing technique is also used to cut down the critical path delay, especially in the recursive radix-4 address generator. From synthesis result, this work can operate at 405 MHz to offer decoding data rate up to 510 Mbps in 90nm CMOS technology.