A study into high-throughput decoder architectures for high-rate LDPC codes

This study investigates a variety of high-throughput decoder architectures designed for high-rate low-density parity-check (LDPC) codes. To implement a high-throughput decoder, a fully-parallel architecture can be adopted, but with complex interconnections. In order to reduce the routing complexity, a Split-Row Threshold decoder can be adopted. However, the high check-node degree of a high-rate LDPC code leads to a long critical path when using the Split-Row Threshold decoder. The long critical path can be shortened by using partially-parallel architectures combined with vertical scheduling. Two-phase message passing and shuffled message passing can be adopted in the vertical scheduling. The features of these state-of-the-art high-throughput decoder architectures and the associated comparison are presented in this paper.