Title :
Low jitter hybrid Phase Locked Loop
Author :
Raj, R.P. ; Balaji, S. ; Srinivasan, K.S. ; Senthilnathan, S.
Author_Institution :
Dept. of ECE, Easwari Eng. Coll., Chennai, India
fDate :
Nov. 30 2012-Dec. 1 2012
Abstract :
In this paper, we present Low jitter hybrid Phase Locked Loop (PLL). PLL are widely used in digital communication receivers because they generate a necessary clock signal, the PLLs used in communication receivers require to generate a low-jitter clock with fast frequency and phase lock. Our hybrid PLL (HPLL) architecture consists of a LC-PLL followed by a Ring-PLL. The HPLL achieves improved jitter performance with a wide frequency range. The Ring PLL noise performance is improved using an LCPLL as a reference clock generator.
Keywords :
clocks; jitter; phase locked loops; LC-PLL; clock signal; digital communication receivers; fast frequency lock; hybrid PLL architecture; hybrid phase locked loop; jitter performance; low-jitter clock; reference clock generator; ring-PLL; Active inductors; CMOS integrated circuits; Charge pumps; Clocks; Jitter; Phase locked loops; Voltage-controlled oscillators; Jitter; LCPLL; RingPLL;
Conference_Titel :
Emerging Applications of Information Technology (EAIT), 2012 Third International Conference on
Conference_Location :
Kolkata
Print_ISBN :
978-1-4673-1828-0
DOI :
10.1109/EAIT.2012.6408017
