Estimation of high speed encoder with MTCMOS technique in 45 nanometer era

Author

Akashe, Shyam ; Rajak, V. ; Sharma, Gitika ; Pandey, Rashmi

Author_Institution

ITM Univ., Gwalior, India

fYear

2012

fDate

Oct. 30 2012-Nov. 2 2012

Firstpage

22

Lastpage

26

Abstract

High performance 4:2 Encoder design using standard CMOS (Complementary Metal Oxide Semiconductor) logic gates is proposed. The proposed encoder design implementation accommodates both high and low current/power characteristics with scalable design structure through MTCMOS (Multi threshold CMOS) technique. This technique is applied to minimize the entire power and shows significant improvement in terms of speed. During the simulation we simulate the encoder by regular CMOS scheme and then proposed MTCMOS technique consists of sleep transistors connect with the logic circuit. The leakage current reduces to 54.56% and leakage power is 57.71%.

Keywords

CMOS logic circuits; logic gates; MTCMOS technique; complementary metal oxide semiconductor; encoder design; high speed encoder; logic circuit; multithreshold CMOS; nanometer era; size 45 nm; sleep transistors; standard CMOS logic gates; CMOS integrated circuits; CMOS technology; Leakage current; Logic gates; Power demand; Threshold voltage; Transistors; CMOS; Encoder; Leakage current; Leakage power; MTCMOS;

fLanguage

English

Publisher

ieee

Conference_Titel

Information and Communication Technologies (WICT), 2012 World Congress on

Conference_Location

Trivandrum

Print_ISBN

978-1-4673-4806-5

Type

conf

DOI

10.1109/WICT.2012.6409044

Filename

6409044