Efficient multi-bit SRAMs using spatial wavefunction switched (SWS)-FETs

Author

Gogna, P. ; Lingalugari, M. ; Chandy, John ; Jain, Faquir C. ; Heller, Eric ; Hasaneen, E.

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Connecticut, Storrs, CT, USA

fYear

2012

fDate

7-9 Aug. 2012

Firstpage

1

Lastpage

4

Abstract

This paper presents the multiple quantum well channel spatial wavefunction switched FETs (SWS-FETs) configured to implement multi-bit static random access memory (SRAM) cells. A 2-bit SRAM cell consists of two back-to-back connected 4-channel SWS-FETs, where each SWS-FET serves as quaternary inverter. This architecture results in reduction of FET count by 75% and data interconnect density by 50%. The designed 2-bit SRAM cell is simulated using BSIM equivalent channel models (for 25nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS-SRAM technology. Quantum simulations for Si/Ge and InGaAs-based SWS-FETs are also presented.

Keywords

Ge-Si alloys; III-V semiconductors; SRAM chips; field effect transistors; gallium compounds; indium compounds; invertors; BSIM equivalent channel models; FET count; InGaAs; SRAM; SiGe; binary interface logic; conversion circuitry are; data interconnect density; multibit static random access memory cells; quantum well channel spatial wavefunction switched FET; quaternary inverter; size 25 nm; FETs; Indium gallium arsenide; Inverters; Logic gates; SRAM cells; Silicon; Multi Bit SRAM; SWS-FET;

fLanguage

English

Publisher

ieee

Conference_Titel

Lester Eastman Conference on High Performance Devices (LEC), 2012

Conference_Location

Singapore

Print_ISBN

978-1-4673-2298-0

Electronic_ISBN

978-1-4673-2300-0

Type

conf

DOI

10.1109/lec.2012.6410969

Filename

6410969