DocumentCode :
591402
Title :
Variation mitigation technique in SRAM cell using adaptive body bias
Author :
Kushwaha, Supriya ; Prasad, Santasriya ; Islam, Aminul
Author_Institution :
Dept. of Electron. & Commun. Eng., Birla Inst. of Technol., Ranchi, India
fYear :
2012
fDate :
28-29 Dec. 2012
Firstpage :
117
Lastpage :
120
Abstract :
This paper presents a circuit technique for designing a variability aware SRAM cell operable at near threshold region. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that DTMOS is used for the access FETs and DSBB (dynamically swapped body bias) scheme is used for feedback and feed-forward inverters of the cell. In this work, various design metrics of the proposed design are assessed and compared with conventional 6T at iso-device area.
Keywords :
SRAM chips; field effect transistors; integrated circuit design; invertors; DSBB; access FET; adaptive body bias; dynamically swapped body bias; feed-forward inverters; feedback inverters; near threshold region; standard 6T SRAM cell; variability aware SRAM cell; variation mitigation; Decision support systems; Intelligent systems; Random access memory; Redundancy; Solid state circuits; Solids; System-on-a-chip; DIBL; RDF; RSNM; SRAM; Variability;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Devices and Intelligent Systems (CODIS), 2012 International Conference on
Conference_Location :
Kolkata
Print_ISBN :
978-1-4673-4699-3
Type :
conf
DOI :
10.1109/CODIS.2012.6422150
Filename :
6422150
Link To Document :
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