Variation mitigation technique in SRAM cell using adaptive body bias

This paper presents a circuit technique for designing a variability aware SRAM cell operable at near threshold region. The architecture of the proposed cell is similar to the standard 6T SRAM cell with the exception that DTMOS is used for the access FETs and DSBB (dynamically swapped body bias) scheme is used for feedback and feed-forward inverters of the cell. In this work, various design metrics of the proposed design are assessed and compared with conventional 6T at iso-device area.