Design of high delay block using voltage scaling technique

Delay blocks are an important building block of signal processing circuits. To a great extent, performance of such circuits depend on the efficient design of delay blocks. In this work, a new scheme for designing a high delay chain is presented precisely for low frequency applications. The proposed design is based on the fact that propagation delay of a CMOS inverter increases with scaling down of supply voltage. This technique is highly area and power efficient as compared to other commonly used techniques. Designing of Ring Oscillator and Non-Overlapping-Clock (NOC) generator with the proposed scheme is also demonstrated. Designs are simulated on UMC 180 nm CMOS process with 1.8 V supply. Simulation results presented here strongly support the analysis done throughout the work. It is also shown that as the frequency of operation reduces, the proposed scheme becomes more and more advantageous. PVT analysis confirm the rigidity of the architecture.