Implementation and Evaluation of Modular Multiplication Based on Coarsely Integrated Operand Scanning

RSA encryption is widely used in public crypto systems. However, according to recent development of computer processing, decipher can be executed in 512-bit key length. Therefore, it has been recommended to move to RSA 2048 from RSA 1024. However, as key length increases, the amount of computation is increased for encryption. Consequently, we consider hardware implementation of processing units. In hardware implementation, the processing speed and circuit size is a trade-off relationship. In embedded devices as the IC card reader, severe resource constraints will be imposed. In this paper, based on Coarsely Integrated Operand Scanning, which is one of Montgomery multiplication, we suggest the modular multiplication circuit architecture for adjusting the trade-off processing speed and circuit size. We design modular multiplication circuit using the proposed architecture at 4-radix. Utilization for the circuit as follows: 146 slices, 461 registers, 685 look-up tables, which allows a compact implementation on the FPGA with Spartan-6 XC6SLX45T. As results, maximum operating frequency is 213.022[MHz], processing time is 41.47[μs], it was achieved 30 times faster compared with software processing.