PAAG: A Polymorphic Array Architecture for Graphics and Image Processing

Author

Tao Li ; Lingzhi Xiao ; Hucai Huang ; Jungang Han

Author_Institution

Res. Center for Telecom ASIC Design, Xi´An Univ. of Posts & Telecom, Xi´An, China

fYear

2012

fDate

17-20 Dec. 2012

Firstpage

242

Lastpage

249

Abstract

A novel, polymorphic array architecture is proposed in this paper. This architecture is capable of supporting a dynamic mixture of data parallel computation (DLP), thread level parallel computation (TLP), and operation level parallel computation (OLP). We aim at designing a programmable architecture that can approach ASIC performance. This is accomplished through new architectural features and implementation level innovations. The architecture and its implementation are presented in the paper to demonstrate its feasibility and capabilities.

Keywords

application specific integrated circuits; computer graphics; image processing; multi-threading; parallel architectures; ASIC performance; DLP; OLP; PAAG; TLP; data parallel computation; dynamic mixture; graphics processing; image processing; implementation level innovations; operation level parallel computation; polymorphic array architecture; programmable architecture; thread level parallel computation; Application specific integrated circuits; Arrays; Instruction sets; Message systems; Parallel processing; Pipelines; Parallel computation; data parallelism; message routing; operation level parallelism; polymorphic architecture; thread level parallelism; thread scheduling;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Architectures, Algorithms and Programming (PAAP), 2012 Fifth International Symposium on

Conference_Location

Taipei

ISSN

2168-3034

Print_ISBN

978-1-4673-4566-8

Type

conf

DOI

10.1109/PAAP.2012.53

Filename

6424763