A Design Flow for FPGA Partial Dynamic Reconfiguration

With the rapid development of very large scale integration (VLSI), FPGA exposed many limitations at the speed and chip capacity. FPGA dynamic reconfiguration technology combined with the both advantages of General Purpose Processor(GPP) and Application Specific Integrated Circuits (ASIC), and this is the key point to improve the flexibility of FPGA and ASIC. Due to the lack of a proven design flow, dynamic partial reconfiguration technology development and application are limited. In this paper, three existing dynamic reconfigurable technology have been analyzed at first, and then a dynamic reconfigurable encryption system has been designed as the target system. The main contribution of this paper is in proposing a complete design flow of the dynamic partial reconfiguration technology. The key steps of the implementation process on Xilinx Virtex5 development platform have been analyzed specially. It is shown in the experiment that about 40% resource optimization was brought and the flexibility of the system was improved greatly by the dynamic partial reconfiguration.