A greedy approach for floopanning mass modules

Because of its efficiency in evaluating area cost and perturbation, slicing structure had been widely used to represent a floorplan in a VLSI decades ago. Due to the possibility of relatively higher dead space, slicing structure is almost replaced by non-slicing structure to represent a floorplan or placement now. However, with the fast growing of chip complexity, the amount of modules/transistors in a chip lengthens the computation time for flooplanning dramatically. Besides, since the dimension of bounding box should be fixed, the constraint of dead space in a floorplan is not as tight as we thought before. In other words, it is possible that slicing structure is a good representation for floorpan with mass modules. For a slicing structure, we propose a greedy approach with a relaxed Polish expression and implement our approach based on simulated annealing algorithm. The experimental results show that the proposed approach works efficiently and the result is competent.