Low power TG full adder design using CMOS nano technology

Author

Sharma, Ashok ; Singh, Rajdeep ; Mehra, Rajesh

Author_Institution

Dept. of Electron. & Commun. Eng., Nat. Inst. of Tech. Teachers Training & Res., Chandigarh, India

fYear

2012

fDate

6-8 Dec. 2012

Firstpage

210

Lastpage

213

Abstract

Full adders is the basic building block of ALU and ALU is a basic functioning unit of the microprocessors and DSP. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption. In this paper transmission gates have been used to develop the proposed full adder using 6 transistors XOR gates. The carry logic has been efficiently implemented using 2×1 MUX to reduce transistor count. The reduction in Transistor count results in improved area and power consumption. The proposed full adder has been designed using 27 and 18 transistors using 90 nm technologies. The developed adder with 18 transistors has shown an improvement of 6.624% in power and 31.765% in area so as to implement adder efficiently in digital signal processors.

Keywords

CMOS integrated circuits; adders; logic gates; nanoelectronics; transistors; 2x1 MUX; CMOS nanotechnology; carry logic; digital signal processor; low power TG full adder design; power consumption; size 90 nm; transistor XOR gate; transistor count; transmission gate; CMOS integrated circuits; CMOS technology; Design methodology; MOS devices; Nanotechnology; Transistors; DSCH; full adder; transmission gate (TG) very Large-scale integration (VLSI);

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Distributed and Grid Computing (PDGC), 2012 2nd IEEE International Conference on

Conference_Location

Solan

Print_ISBN

978-1-4673-2922-4

Type

conf

DOI

10.1109/PDGC.2012.6449819

Filename

6449819