On improving the performance of Traff´s comparator

In this paper a new current comparator is proposed which offers high speed and high resolution while maintaining low power dissipation. The design improves upon previous Traff current comparator by modifying the given gain stage which leads to up to 83% improvement in delay. Simulation results performed on SPICE using TSMC 0.18μm CMOS technology demonstrate that proposed current comparator has a resolution of ± 10nA and delay of 0.86ns at ± 1μA input current. Performance for lower supply voltages is also reported.