FPGA implementation of high speed multiplier using higher order compressors

In general applications such as image processing signal processing and many similar applications find most of the work is done through multipliers to execute complex instructions. We generally use low order compressors for this multiplication operations. In this proposed paper, we are using higher order compressors to execute the multiplication operation. As these compressors have less delay, low power consumption but also occupies slightly larger area and this helps in incrementing of execution speed of whole multiplier.