DocumentCode
593864
Title
Low complexity hardware architectural design for adaptive decision feedback equalizer using distributed arithmetic
Author
Prakash, M. Sunil ; Shaik, Rafi Ahamed
Author_Institution
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
fYear
2012
fDate
18-20 Dec. 2012
Firstpage
1
Lastpage
5
Abstract
In this paper, we propose a low complex architectural design for adaptive decision feedback equalizer (ADFE). For this we recast the ADFE equations using distributed arithmetic (DA), which enables the implementation of ADFE without multipliers. The design is based on the distributed arithmetic based formulation of it. It is further shown that high order filters, which are required to implement high speed ADFEs can be realized using only look-up-tables (LUTs) and shift-accumulate operations. A novel approach was proposed to replace feed forward and feedback filters of ADFE with a single DA unit. By proper initialization, it is also shown that a low complexity ADFE architecture can be obtained.
Keywords
adaptive equalisers; adaptive filters; decision feedback equalisers; table lookup; adaptive decision feedback equalizer; distributed arithmetic based formulation; feed forward filters; feedback filters; high order filters; look-up-tables; low complexity hardware architectural design; shift-accumulate operations; Complexity theory; Decision feedback equalizers; Field-flow fractionation; Hardware; Table lookup; Vectors; Adaptive Decision Feedback Equalizer (ADFE); Distributed Arithmetic (DA); Inter Symbol Interference (ISI); Least Significant Bit (LSB); Most Significant Bit (MSB); quantization; slicer;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Systems and Industrial Informatics (ICCSII), 2012 International Conference on
Conference_Location
Sharjah
Print_ISBN
978-1-4673-5155-3
Type
conf
DOI
10.1109/ICCSII.2012.6454433
Filename
6454433
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