Title :
Measurement of SSO noise and PDN impedance of 3D SiP with 4k-IO widebus structure
Author :
Tanaka, Yuichi ; Takatani, Hiroki ; Fujita, Hideaki ; Oizono, Y. ; Nabeshima, Yuji ; Sudo, Toshio ; Sakai, Akihiko ; Uchiyama, S. ; Ikeda, Hinata
Author_Institution :
Shibaura-Inst. of Technol., Tokyo, Japan
Abstract :
Simultaneous switching output buffer (SSO) noise and impedance of power distribution network (PDN) for a 3D systemin package (SiP) with 4k-IO widebus structure has been investigated. The 3D SiP consisted of 3 stacked chips and an organic interposer. These three chips were a memory chip on the top, a silicon interposer in the middle, and a logic chip on the bottom. The size of each chip was the same, and 9.93 mm by 9.93 mm. More than 4096 of through silicon vias (TSV´s) were formed to the silicon interposer. Next, these 3 stacked chips were assembled on the organic interposer, whose size was 26 mm by 26mm. SSO noise is one of critical issues for the 3D SiP with 4k-IO widebus structure. So, the SSO noise was measured in the miniIO power supply system in an evaluation board. Furthermore the PDN impedance for each chip was measured by direct contact method. Then, the total PDN impedance was synthesized to confirm the anti-resonance peak of it.
Keywords :
integrated circuit noise; system-in-package; three-dimensional integrated circuits; 3D SiP; 3D system in package; 4k-IO widebus structure; PDN impedance; SSO noise measurement; TSV; direct contact method; logic chip; memory chip; organic interposer; power distribution network; silicon interposer; stacked chips; switching output buffer; through silicon vias; Frequency measurement; Impedance; Impedance measurement; Noise; Semiconductor device measurement; Silicon; Substrates;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on
Conference_Location :
Tempe, AZ
Print_ISBN :
978-1-4673-2539-4
Electronic_ISBN :
978-1-4673-2537-0
DOI :
10.1109/EPEPS.2012.6457850
