Title :
Findings and considerations for I/O clock jitter on a source synchronous front side bus
Author :
Dreps, Daniel ; Daniels, Laura ; Mandrekar, R. ; Pham, N. ; Lei Shan
Author_Institution :
IBM STG, Austin, TX, USA
Abstract :
This paper outlines when designing a front side bus that is source synchronous the clock needs special consideration. If the clock is treated the same as data bit the bus performance or bit rate can be limited by the clock distortion effects. Investigations of the components of the distortion are described along with prevention rules and silicon architecture impacts.
Keywords :
clocks; elemental semiconductors; jitter; silicon; I-O clock jitter; Si; clock distortion effect; data bit rate; prevention rule; silicon architecture impact; source synchronous front side bus; Clocks; Connectors; Crosstalk; Jitter; Noise; Silicon; Synchronization; Clock Jitter; Front Side Bus; Source Synchronous;
Conference_Titel :
Electrical Performance of Electronic Packaging and Systems (EPEPS), 2012 IEEE 21st Conference on
Conference_Location :
Tempe, AZ
Print_ISBN :
978-1-4673-2539-4
Electronic_ISBN :
978-1-4673-2537-0
DOI :
10.1109/EPEPS.2012.6457907
