Design and error analysis of a scale free CORDIC unit with corrected scale factor

This paper presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures. The analysis of error for different word lengths and different input ranges for fixed word length gives a better choice to choose the parameters. The error in rotation mode for 16 bit data path, obtained for ordinate equivalent input is 0.073% and for abscissa equivalent input is 0.067%. The proposed design implemented in Xilinx XC3S500E-4FG320 FPGA, fabricated in 90 nm process technology, consumes 503 slices and 984 4-input look up tables (LUTs). The proposed design has a maximum frequency of operation of 75.593 MHz and a slice delay product of 104.645.