• DocumentCode
    594242
  • Title

    Design of an ultra-low powered DC-DC buck converter for wireless sensor networks

  • Author

    Sarkar, Santonu ; Maity, Avisek ; Patra, Abani

  • Author_Institution
    Electr. Eng. Dept., IIT Kharagpur, Kharagpur, India
  • fYear
    2012
  • fDate
    5-7 Dec. 2012
  • Firstpage
    126
  • Lastpage
    131
  • Abstract
    Wireless sensor networks (WSNs) are normally installed in remote, inaccessible locations. Energy harvesting technique is used in such systems which periodically charges the battery automatically. The life-cycle of such a rechargeable battery depends on the number of charge/discharge cycles. To prolong the battery life, an ultra-low powered DC-DC converter, which interfaces between the battery and the load, is required. This paper describes an ultra-low powered, switched capacitor based DC-DC buck converter, in 180 nm standard CMOS technology, targeted for WSN applications. The input voltage can vary from 2.1-4.5 V and the output voltage to be regulated is 1.8 V. The load requires a maximum of 4 mA of load current for 15 ms of on-time, and thereafter a mere 2 μA for 3 minutes of sleep time. The duty cycle of the clock is typically of the order of 1:12000 or even more, and the typical average output power is around 4.2 μW. In this design, an ultra low quiescent current of 500 nA for the whole converter is achieved over a desired load range of 0.002-4 mA. Consequently, the peak power efficiency has been improved by 20% compared to existing designs. Also, a unique low power consuming two-phase non-overlapping clock generation circuit with an adjustable skew margin is designed. A basic block diagram of this circuit is described.
  • Keywords
    CMOS integrated circuits; DC-DC power convertors; clocks; low-power electronics; wireless sensor networks; WSN applications; adjustable skew margin; basic block diagram; charge-discharge cycles; current 0.002 mA to 4 mA; efficiency 20 percent; energy harvesting technique; life-cycle; rechargeable battery; size 180 nm; standard CMOS technology; switched capacitor based buck converter; time 15 ms; time 3 min; two-phase non-overlapping clock generation circuit; ultra-low powered dc-dc buck converter design; voltage 1.8 V; wireless sensor networks; Capacitors; Clocks; Hysteresis; Mathematical model; Switches; Topology; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in
  • Conference_Location
    Hyderabad
  • ISSN
    2159-2144
  • Print_ISBN
    978-1-4673-5065-5
  • Type

    conf

  • DOI
    10.1109/PrimeAsia.2012.6458640
  • Filename
    6458640