Title :
High-speed architecture for Advanced Encryption Standard Algorithm
Author :
Rachh, R.R. ; AnandaMohan, P.V. ; Anami, Basavaraj S.
Author_Institution :
Dept. of Comput. Sci., KLESCET, Belgaum, India
Abstract :
This paper presents high speed architecture for AES encryption. The proposed architecture uses integrated unit of encryption in which the consecutive transformations of AES are integrated into a single unit to arrive at an architecture with shorter critical path. Further reduction in critical path is achieved by applying pre-computation technique. Synthesis results using Synopsis 0.18 μm CMOS process are also provided to substantiate the claims.
Keywords :
CMOS integrated circuits; cryptography; AES encryption; Synopsis CMOS process; advanced encryption standard algorithm; high-speed architecture; integrated unit; precomputation technique; size 0.18 mum; Asia; Computer architecture; Delay; Encryption; Logic gates; Microelectronics; Multiplexing; AES; Encryption; critical path; cryptosystems; decryption; implementation; pre-computation;
Conference_Titel :
Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in
Conference_Location :
Hyderabad
Print_ISBN :
978-1-4673-5065-5
DOI :
10.1109/PrimeAsia.2012.6458647
