A high-speed reversible low-power Error Tolerant Adder

A new reversible Error Tolerant Adder (ETA) based on the reversible Logic is proposed. RH and RS gates are the novel reversible logic gates based on which the ETA is designed. The reversible 3×3 RH gate is derived from existing 2×2 quantum gates - CNOT, Controlled-V and Controlled-V⁺. The reversible 3×3 RS gate consists of the existing CNOT and Peres Quantum gates. The design of the proposed reversible ETA demonstrates better power delay product (PDP) than the existing ETA´s in terms of quantum cost and delay, while maintaining the minimum number of garbage outputs. In comparison with other ETAs, the current design offers a PDP improvement of 54.06%.