A high-speed reversible low-power Error Tolerant Adder

Author

Raheem, M.A. ; Gupta, H. ; Fatima, Kaleem ; Adil, O.

Author_Institution

ECE Dept., Muffakham Jah Coll. of Eng. & Technol., Hyderabad, India

fYear

2012

fDate

5-7 Dec. 2012

Firstpage

178

Lastpage

183

Abstract

A new reversible Error Tolerant Adder (ETA) based on the reversible Logic is proposed. RH and RS gates are the novel reversible logic gates based on which the ETA is designed. The reversible 3×3 RH gate is derived from existing 2×2 quantum gates - CNOT, Controlled-V and Controlled-V⁺. The reversible 3×3 RS gate consists of the existing CNOT and Peres Quantum gates. The design of the proposed reversible ETA demonstrates better power delay product (PDP) than the existing ETA´s in terms of quantum cost and delay, while maintaining the minimum number of garbage outputs. In comparison with other ETAs, the current design offers a PDP improvement of 54.06%.

Keywords

adders; quantum gates; CNOT; ETA; PDP improvement; Peres quantum gates; RH gates; RS gates; controlled-V; controlled-V⁺; high-speed reversible low-power error tolerant adder; power delay product; quantum cost; quantum gates; reversible logic gates; Accuracy; Adders; Asia; Delay; Logic gates; Microelectronics; Vectors; Accuracy; Error Tolerance; Garbage Outputs; High Speed Circuits; Low Power Design; Quantum Cost; Reversible Logic;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in

Conference_Location

Hyderabad

ISSN

2159-2144

Print_ISBN

978-1-4673-5065-5

Type

conf

DOI

10.1109/PrimeAsia.2012.6458649

Filename

6458649