Fabrication Process and Properties of Fully-Planarized Deep-Submicron Nb/Al– Josephson Junctions for VLSI Circuits

A fabrication process for Nb/Al-AlO_x/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO₂ interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, I_c, normal-state conductance, G_N, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, J_c, from 10 kA/cm² to 50 kA/cm² where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The G_N and I_c spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. I_c and G_N spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > 10⁶ JJ/cm² and 193-nm photolithography for JJ definition are discussed.