DocumentCode
59445
Title
An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at
0 V Achieving Zero Leakage With
https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=59445
-based 32-b microcontroller system-on-chip (SoC) that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400 ns to restore the system state upon power-up. Nonvolatile Fe-Cap-based mini-arrays backup the machine state and allow the chip to wake up instantly after a power cycle. Without NVL, a chip would either have to keep all flip-flops powered, resulting in high standby power, or waste energy and time rebooting after power-up. NVL allows systems to use leakier processes to achieve higher performance/lower dynamic power while still having zero leakage in the sleep mode. Optimized system, architecture, and circuit techniques are presented that make NVL practical by adding only 3.6% to the SoC area. Since nonvolatile elements are added to the SoC, reliability and testability have to be key features of the design. This is the first NVL SoC with measured NVL bitcell read signal margin data and extensive test and debug capabilities. The chip is fabricated in a commercial 130-nm low-leakage process and uses a single 1.5-V power supply.</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Keywords</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>ferroelectric storage; flip-flops; integrated circuit design; integrated circuit manufacture; integrated circuit reliability; integrated circuit technology; integrated circuit testing; logic circuits; microcontrollers; random-access storage; system-on-chip; FRAM-based nonvolatile logic MCU SoC; NVL; NVL bitcell read signal margin data measurement; ULP application; debug capability; digital state retention; ferroelectric RAM; flip-flop; low-leakage process; machine state; microcontroller; nonvolatile Fe-Cap-based mini-array; performance-lower dynamic power; power interruption; reliability; size 130 nm; sleep mode; system-on-chip; testability; voltage 1.5 V; waste energy; zero leakage; Arrays; Capacitors; Ferroelectric films; Nonvolatile memory; Random access memory; System-on-chip; Ferroelectric RAM (FRAM); low power; microcontrollers; nonvolatile logic (NVL);</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>fLanguage</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>English</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Journal_Title</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>Solid-State Circuits, IEEE Journal of</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>ISSN</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>0018-9200</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Type</span></div><div class='col-12 col-md-9 leftDirection leftAlign'><h2 class='mb-0 fw-semibold'>jour</h2></div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>DOI</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>10.1109/JSSC.2013.2284367</div></div>
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<div class='row g-0 align-items-center mb-2'><div class='col-12 col-md-3 fullRecLabelEnglish fw-bold mb-2 mb-md-0'><span class='text-muted small'>Filename</span></div><div class='col-12 col-md-9 leftDirection leftAlign'>6637100</div></div>
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https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=59445