Title :
Graphically Transforming Mueller-Schulz Percolation Criteria to Random Telegraph Signal Magnitudes in Scaled FETs
Author :
Ming-Jer Chen ; Kong-Chiang Tu ; Li-Yang Chuang ; Huan-Hsiung Wang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
We propose a novel graphic method to enable the analysis of the field-effect transistor (FET) threshold voltage variation ΔVth due to random telegraph signals in a percolative channel. First, through technology computer-aided design simulation with no percolation, both a minimum ΔVth and a critical curve in a mloc - σloc plot are produced. The former constitutes a statistical distribution far away from the conventional log-normal one. In the latter, mloc and σloc are the mean and the standard deviation, respectively, of a well-known normal variable in Mueller-Schulz´s percolation theory. The critical mloc - σloc curve divides the plot into the allowed region and the forbidden region and will go down with increasing gate size. Then, ΔVth contours in the allowed region are graphically created. While applying to existing experimental ΔVth statistical distributions of SiON- and high-k metal gate (HKMG)-scaled FETs, resulting paired mloc and σloc at high ΔVth remain intact, regardless of gate size or gate stack type. This means that the underlying percolation patterns resemble each other, due to the same manufacturing process used. However, if these paired mloc and σloc fall in the forbidden region, it is the critical mloc - σloc curve dominating. Application to bias and temperature instability statistical data in literature is straightforwardly well done.
Keywords :
field effect transistors; negative bias temperature instability; percolation; statistical distributions; FET threshold voltage variation; HKMG-scaled FET; Mueller-Schulz percolation criteria; Mueller-Schulz´s percolation theory; allowed region; bias and temperature instability statistical data; critical curve; field-effect transistor threshold voltage variation; forbidden region; high-k metal gate-scaled FET; mean deviation; percolation patterns; percolative channel; random telegraph signals; standard deviation; statistical distribution; technology computer-aided design simulation; Field effect transistors; Graphics; Logic gates; Noise; Standards; Statistical distributions; Bias and temperature instability (BTI); field-effect transistors (FETs); fluctuations; percolation; random telegraph signals (RTSs); technology computer-aided design (TCAD); trap;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2015.2388787