• DocumentCode
    596085
  • Title

    A formal model of a large memory that supports efficient execution

  • Author

    Hunt, Warren A. ; Kaufmann, Matt

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Texas, Austin, TX, USA
  • fYear
    2012
  • fDate
    22-25 Oct. 2012
  • Firstpage
    60
  • Lastpage
    67
  • Abstract
    The validation and application of formal processor models benefits fundamentally from both efficient execution and automated reasoning about the models. We present a memory model written in the ACL2 logic, with both reasoning support and a runtime environment, that accomplishes these objectives. Our memory model provides a space-efficient implementation for an address space of 248 bytes, and is used in our development of an ISA model for x86 instructions. We define and prove invariants, and we use them to prove useful lemmas and to formally verify absence of run-time simulator errors. Our memory model also supports efficient execution through constant-time read and write access in an applicative setting.
  • Keywords
    formal logic; formal verification; instruction sets; ACL2 logic; ISA model; address space; automated reasoning; constant-time read and write access; formal model; formal processor models; formally verification; memory model written; reasoning support; run-time simulator errors; runtime environment; space-efficient implementation; x86 instructions; Arrays; Ash; Computational modeling; Design automation; Indexes; Memory management; Microprocessors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Formal Methods in Computer-Aided Design (FMCAD), 2012
  • Conference_Location
    Cambridge
  • Print_ISBN
    978-1-4673-4832-4
  • Type

    conf

  • Filename
    6462556