Title :
Decompilation into logic — Improved
Author :
Myreen, M.O. ; Gordon, M.J.C. ; Slind, K.
Author_Institution :
Comput. Lab., Univ. of Cambridge, Cambridge, UK
Abstract :
This paper presents improvements to a technique which aids verification of machine-code programs. This technique, called decompilation into logic, allows the verifier to only deal with tractable extracted models of the machine code rather than the concrete code itself. Our improvements make decompilation simpler, faster and more generally applicable. In particular, the new technique allows the verifier to avoid tedious reasoning directly in the underlying machine-code Hoare logic or the model of the instruction set architecture. The method described in this paper has been implemented in the HOL4 theorem prover.
Keywords :
formal logic; instruction sets; program verification; theorem proving; HOL4 theorem prover; decompilation into logic; instruction set architecture; machine-code Hoare logic; machine-code program verification; Arrays; Assembly; Cognition; Computational modeling; Concrete; Design automation;
Conference_Titel :
Formal Methods in Computer-Aided Design (FMCAD), 2012
Conference_Location :
Cambridge
Print_ISBN :
978-1-4673-4832-4