• DocumentCode
    59630
  • Title

    Optimizing Task and Data Assignment on Multi-Core Systems with Multi-Port SPMs

  • Author

    Shouzhen Gu ; Qingfeng Zhuge ; Juan Yi ; Jingtong Hu ; Sha, Edwin Hsing-Mean

  • Author_Institution
    Coll. of Comput. Sci., Chongqing Univ., Chongqing, China
  • Volume
    26
  • Issue
    9
  • fYear
    2015
  • fDate
    Sept. 1 2015
  • Firstpage
    2549
  • Lastpage
    2560
  • Abstract
    Multi-core processors have been adopted in modern embedded systems to meet the ever increasing performance requirements. Scratchpad memory (SPM), a software-controlled on-chip memory, has been used in embedded systems as an alternative to hardware-controlled cache due to its advantage in die area, power consumption, and timing predictability. SPMs in multi-core systems can be accessed by both local core and remote cores. In order to alleviate data contention on a SPM unit, multi-port SPMs are employed in multi-core systems. In such systems, proper task scheduling and data assignment can significantly improve the overall performance by exploring the parallelism of computation tasks and concurrent data accesses on SPMs. Since scheduling for multi-core systems is NP-Complete in general. In this paper, we propose an ILP formulation to optimally determine the task scheduling and data assignment on multi-core systems with multi-port SPMs. Since ILP takes exponential time to finish, we also propose a heuristic method, including the task assignment with remote access reduced (TARAR) algorithm and the minimum memory access cost (MMAC) algorithm, to obtain near optimal solutions within polynomial time. According to the experimental results, the ILP formulation can improve the system performance by 23.02 percent over the HAFF algorithm on average, while the heuristic algorithm can improve the system performance by 16.48 percent over HAFF on average.
  • Keywords
    microprocessor chips; multiprocessing systems; polynomials; ILP formulation; MMAC algorithm; TARAR algorithm; data assignment; embedded systems; minimum memory access cost; multicore processors; multicore systems; multiport SPM; optimizing task; polynomial time; scratchpad memory; software controlled onchip memory; task assignment with remote access reduced; Clocks; Heuristic algorithms; Multicore processing; Optimal scheduling; Schedules; System-on-chip; Task scheduling; data assignment; multi-core systems; multi-port SPMs; scheduling;
  • fLanguage
    English
  • Journal_Title
    Parallel and Distributed Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1045-9219
  • Type

    jour

  • DOI
    10.1109/TPDS.2014.2356194
  • Filename
    6894167