• DocumentCode
    596543
  • Title

    Design and implementation of the multicore architecture teaching experiment platform

  • Author

    Qian Wang ; Yuhua Tang ; Zongbo Li ; Jin Wang

  • Author_Institution
    State Key Lab. of High Performance Comput., Nat. Univ. of Defense Technol., Changsha, China
  • fYear
    2012
  • fDate
    18-20 Oct. 2012
  • Firstpage
    72
  • Lastpage
    78
  • Abstract
    With the continuous improvement of integrated circuit technology, the new low-power, multicore architecture to replace the previous single core processor architecture has become an inevitable trend of development. The emergence of multicore architectures will lead teaching courses face the problem that the experiments contents should be updated. Under such demand, this article reforms the teaching experiments on the computer architecture courses and completes design and implementation of a multicore architecture computer experiment platform based on Tianhe Sunshine development board. This article makes an analysis of Beehive experiment platform which is based on the XUPV5 development board. On this basis, according to Tianhe Sunshine development board´s hardware configuration, we design single core processor, DDR controller and the communication module which can exchange information between PC and board, complete the multicore architecture teaching experiment platform based on message passing model. Finally, this article simulates and verifies the multicore architecture platform functionality. The results of the test show that the designed modules achieved their functions.
  • Keywords
    computer architecture; computer science education; multiprocessing systems; Beehive experiment platform; DDR controller; Tianhe Sunshine development board; XUPV5 development board; communication module; computer architecture courses; hardware configuration; integrated circuit technology; message passing model; multicore architecture computer experiment platform; multicore architecture platform functionality; multicore architecture teaching experiment platform; single core processor architecture; Clocks; Education; Hardware; Multicore processing; Registers; SDRAM;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Computational Intelligence (ICACI), 2012 IEEE Fifth International Conference on
  • Conference_Location
    Nanjing
  • Print_ISBN
    978-1-4673-1743-6
  • Type

    conf

  • DOI
    10.1109/ICACI.2012.6463124
  • Filename
    6463124