Estimating the starting point of conduction in nanoscale CMOS gates

Author

Tzagkas, D. ; Nikolaidis, S. ; Rjoub, Abdoul

Author_Institution

Dept. of Phys., Aristotle Univ. of Thessaloniki, Thessaloniki, Greece

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

957

Lastpage

960

Abstract

In this paper a method for calculating the starting point of conduction of parallel and serial transistor structures in CMOS gates for the nanoscale regime is introduced. The calculation of the starting point is necessary for modeling the operation of complex gates. The influence of the parasitic capacitances is determined and the subthreshold and conducting behavior of the transistors are considered for the analysis of the operation of the serial transistor structure. Appropriate assumptions are used for modeling the circuit operation whose efficiency is determined by the accuracy of the results compared to HSPICE simulations. The overall accuracy of the proposed method is verified through HSPICE simulations for 32nm high k dielectric PTM technology.

Keywords

CMOS logic circuits; MOSFET; high-k dielectric thin films; logic gates; nanoelectronics; HSPICE simulations; circuit operation; complex gates; conducting behavior; conduction starting point; high k dielectric PTM technology; nanoscale CMOS gates; nanoscale regime; parallel transistor structures; parasitic capacitances; serial transistor structures; size 32 nm; subthreshold behavior; Capacitance; Integrated circuit modeling; Logic gates; Mathematical model; Semiconductor device modeling; Subthreshold current; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463502

Filename

6463502