DocumentCode
596792
Title
Design of adaptive nano/CMOS neural architectures
Author
Serrano-Gotarredona, T. ; Linares-Barranco, B.
Author_Institution
Inst. de Microelectron. de Sevilla, CNM, Seville, Spain
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
949
Lastpage
952
Abstract
Memristive devices are a promising technology to implement dense learning synapse arrays emulating the high memory capacity and connectivity of biological brains. Recently, the implementation of STDP learning in memristive devices connected to spiking neurons have been demonstrated as well as the dependency of the form of the learning rule on the shape of the applied spike. In this paper, we propose a fully CMOS integrate-and-fire neuron generating a precisely shaped spike that can be tuned through programmable biases. The implementation of STDP learning is demonstrated through electrical simulations of a 4×4 array of memristors connected to 4 spiking neurons.
Keywords
CMOS memory circuits; circuit simulation; memristors; nanoelectronics; neural chips; STDP learning; adaptive nano/CMOS neural architecture; biological brain connectivity; dense learning synapse array; electrical simulation; fully CMOS integrate-and-fire neuron; learning rule; memory capacity; memristive device; memristor; programmable biases; spiking neuron; CMOS integrated circuits; Memristors; Nanoscale devices; Neurons; Semiconductor device modeling; Shape;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463504
Filename
6463504
Link To Document