A double-delta compensating technique for pulse-frequency modulation CMOS image sensor

Author

Tsung-Hsun Tsai ; Hornsey, Richard

Author_Institution

Dept. of Comput. Sci. & Eng., York Univ., Toronto, ON, Canada

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

945

Lastpage

948

Abstract

We design a double-delta compensating (DDC) technique for a comparator-based pulse-frequency modulation (PFM) pixel. This technique has been demonstrated by simulation to achieve both fixed-pattern noise (FPN) reduction and dynamic range (DR) extension at the high-light region. According to the result, the pixel DR extends by at least 12 dB; FPN is reduced from unacceptable levels to 1-3% when it is caused by the comparator offset voltage or less than 3.5% when the layout and process variations are considered. These simulations have been performed using the Monte Carlo method for realistic parameter variations in a 0.18-μm CMOS technology.

Keywords

CMOS image sensors; Monte Carlo methods; PWM power convertors; comparators (circuits); delta modulation; modulators; pulse frequency modulation; CMOS image sensor; DDC technique; DR extension; FPN reduction; Monte Carlo method; PFM pixel; comparator offset voltage; double-delta compensating technique; dynamic range extension; fixed-pattern noise reduction; pulse-frequency modulation; size 0.18 micron; CMOS image sensors; Dynamic range; Layout; Modulation; Switches; Switching circuits; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463505

Filename

6463505