DocumentCode
596804
Title
A high-throughput ECC architecture
Author
Amini, E. ; Jeddi, Zahra ; Bayoumi, M.
Author_Institution
Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA, USA
fYear
2012
fDate
9-12 Dec. 2012
Firstpage
901
Lastpage
904
Abstract
In this paper, we propose a high-throughput parallel crypto architecture that performs the low level operations for scalar point multiplication over GF(2m) operands. The design performs several different operations in parallel. In the absence of parallel operations or when there are not enough free modules to handle new request, the remaining modules will be deactivated for the sake of power consumption. The experimental results show significant improvement in timing, throughput, and energy performances with a slight overhead in the circuit area.
Keywords
Galois fields; power consumption; public key cryptography; GF(2m) operands; Galois fields; circuit area; elliptic curve cryptography; energy performances; high-throughput ECC architecture; high-throughput parallel crypto architecture; low level operations; power consumption; scalar point multiplication; Clocks; Elliptic curve cryptography; Galois fields; Hardware; Parallel architectures;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location
Seville
Print_ISBN
978-1-4673-1261-5
Electronic_ISBN
978-1-4673-1259-2
Type
conf
DOI
10.1109/ICECS.2012.6463516
Filename
6463516
Link To Document