Complements on phase noise analysis and design of CMOS ring oscillators

This paper reports two complements on phase noise analysis and design of CMOS ring oscillators. In detail, it proposes an extension to current analytical methods for predicting flicker noise contribution to phase noise in differential CMOS ring oscillators. The results of the proposed analysis are compared with the existing methods and simulation results by SpectreRF for two differential topologies. The comparative analyses confirm that the proposed method leads to an improvement of the prediction accuracy in spite of the small increase of complexity since it only requires device dimensions in addition to the data required by existing methods. The proposed method may also be used to indicate a minimum achievable close-in phase noise in a process node. Moreover, a design approach for low phase noise inverter-based ring oscillator is proposed and tested by means of simulation. The limitations of the proposed method can be observed from this case study.