DocumentCode :
596834
Title :
Design of a capacitorless low-dropout voltage regulator with fast load regulation in 130nm CMOS
Author :
Souza, A.D. ; Bampi, Sergio
Author_Institution :
CEITEC-SA Semicond., UFRGS, Porto Alegre, Brazil
fYear :
2012
fDate :
9-12 Dec. 2012
Firstpage :
873
Lastpage :
876
Abstract :
This paper describes a low-dropout (LDO) voltage regulator system for portable device applications, with a capacitorless output. The regulator operates with supply voltages from 1.6V to 2V, providing 0.9V to 1.4V regulated voltages at a 99.2% current efficiency. The fully integrated architecture with a 100pF integrated decoupling capacitor was implemented in IBM 130nm CMOS technology, allowing greater power system integration. Post-layout simulations of our design demonstrate that the proposed LDO architecture provides a fast load regulation with a fast 320ns response time for 100mA load current and regulated voltage variations of less than 25mV.
Keywords :
CMOS integrated circuits; capacitors; integrated circuit layout; voltage regulators; CMOS technology; LDO architecture; capacitorless low-dropout voltage regulator; current 100 mA; fast load regulation; integrated decoupling capacitor; portable device applications; post-layout simulations; size 130 nm; time 320 ns; voltage 0.9 V to 1.4 V; voltage 1.6 V to 2 V; CMOS integrated circuits; Capacitors; Layout; Phase locked loops; Phasor measurement units; Regulators; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
Type :
conf
DOI :
10.1109/ICECS.2012.6463549
Filename :
6463549
Link To Document :
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