An RTL method for hiding clock domain crossing latency

We present an architectural method to hide the latency incurred by synchronization when transferring data between clock domains. Unlike existing solutions, ours does not rely on any timing assumptions between the communicating clocks and is transparent to the design. We demonstrate how to apply the proposed method to a generic Moore machine with an asynchronous port and then describe how this process can be automated by a Register Transfer Level tool. Using an implementation of the tool, we apply our method to six communication controllers and show that it incurs, on average, only 8% of the area of a periodic synchronizer.