Hardware-efficient matrix inversion algorithm for complex adaptive systems

This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively small device as Xilinx Spartan3 XC3S1000, a matrix size up to 23 × 23 can be implemented, having a matrix inversion computation time of 253μs. Accuracy results compared to floating point computation and an estimation of required clock cycles as a function of matrix size are analyzed.