Title :
Uncertainty in DLL deskewing schemes
Author :
Figueiredo, Mauricio ; Aguiar, Rui L.
Author_Institution :
Sch. of Technol. & Manage., Polytech. Inst. of Leiria, Leiria, Portugal
Abstract :
This paper proposes an analytical model to evaluate deskewing uncertainty, considering floorplanning and scalability issues. It can be a helpful tool in evaluating the potential gains of clock deskewing or finding the best deskewing topology for a given application, at an early design stage. Also, we show that all deskewing schemes trade static for dynamic clock uncertainty and thus, our model can be used to determine the maximum tolerable noise levels if a deskewing scheme is to be applied.
Keywords :
delay lock loops; integrated circuit layout; DLL deskewing schemes; clock deskewing; delay-locked loops; deskewing topology; deskewing uncertainty; dynamic clock uncertainty; floorplanning; scalability; tolerable noise levels; Clocks; Delay; Integrated circuit interconnections; Jitter; Synchronization; Topology; Uncertainty;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
DOI :
10.1109/ICECS.2012.6463621
