Flip-flop design using novel pulse generation technique

In this paper, new flip-flop topologies for low power and high-speed digital designs are presented. A novel technique is used to generate a special clock-pulse wave (internally or externally) for flip-flop circuits. This technique shows better characteristics compared to existing techniques in terms of delay and power. The generated pulse is applied to different flip-flop topologies to show the efficacy of the proposed technique on power and speed. Simulation results show improvement in setup time compared to their counterparts. Furthermore, at least 20% improvement in power consumption is observed by utilizing the proposed pulse-generator technique. IBM 65nm Models are used for simulation using CADENCE and Synopsys tools.