A new fault-tolerant architecture for CLBs in SRAM-based FPGAs

This work deals with fault tolerance in digital reconfigurable circuits. We present a novel CLB structure well suited for SRAM-based FPGAs. The proposed solution has a `Butterfly´ shape which embeds intrinsic redundance and is highly regular. The behavior of the proposed Butterfly architecture and that of the conventional one toward bit-inversion errors are compared with a couple of approaches: using Matlab simulations and a fault emulation platform. The Butterfly structure has proved to be more reliable and more tolerant than the conventional counterpart, regardless of the number of simultaneous faults.