Transient fault analysis of CORDIC processor

Author

Ting An ; Causo, M. ; de Barros Naviner, Lirida Alves ; Matherat, Philippe

Author_Institution

Telecom ParisTech, Inst. Mines-Telecom, Paris, France

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

757

Lastpage

760

Abstract

In this paper, we propose a method to evaluate the impact of a transient fault in CORDIC processors. The proposed approach takes into account the spatial and temporal localization of the fault. It also embeds the probability that such a fault occurs. By defining a fault impact coefficient, it is possible to identify the most critical arithmetic blocks and thus to implement an optimized strategy for fault tolerance. We analyzed two structures of CORDIC processors and we showed how to get a better tradeoff between the penalty (area and delay overhead) and the fault tolerant improvement.

Keywords

circuit optimisation; digital arithmetic; fault location; fault tolerance; probability; CORDIC processor; arithmetic block; fault impact coefficient; fault tolerance; fault tolerant improvement; optimized strategy; penalty; probability; spatial fault localization; temporal fault localization; transient fault analysis; Adders; Circuit faults; Computer architecture; Fault tolerance; Fault tolerant systems; Logic gates; Transient analysis; Arithmetic Operators; CORDIC; Fault-tolerance; Selective-Hardening; Transient Fault;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463644

Filename

6463644