The leafs scan-chain for test application time and scan power reduction

A scan-chain architecture that utilizes the existence of don´t care bits (X-bits) in test cubes to provide test application time reduction at reduced power consumption is proposed. According to this scheme the scan-chain is divided into two segments, a first one that retains the shift capability and a second consisting of leaf cells. New test data are shifted in the first segment while only a single clock cycle is used to feed the second segment. In case of X-bits at the test data of the leaf cells the number of shift operations is drastically reduced. Experimental results validate the efficiency of the proposed architecture, which provides test time reductions up to 48%.