Title :
Analysis of coupling capacitance between TSVs and metal interconnects in 3D-ICs
Author_Institution :
Mentor Graphics, Cairo, Egypt
Abstract :
Through-Silicon Via (TSV) is an emerging technology that enables vertical integration of silicon dies forming a single 3D-IC stack. In this paper, the electrical characteristics of coupling between TSVs and metal lines in 3D-ICs are analyzed. The simulation results for the electrical characteristics of the coupling between TSVs and metal lines in 3D-ICs show that the coupling is not negligible when TSV is relatively short compared to the TSV width, where the aspect ratio is less than 5. Therefore, TSV-to-wire capacitance needs to be considered for the computation of TSV capacitance. But, if the aspect ratio is larger than 5, the effect of metal wires is not considered. Moreover, the effect of metal lines on TSV-TSV coupling can be neglected if the pitch is less than 3x the TSV diameter.
Keywords :
coupled circuits; elemental semiconductors; integrated circuit interconnections; silicon; three-dimensional integrated circuits; Si; TSV-TSV coupling; TSV-to-wire capacitance; coupling capacitance analysis; electrical characteristics; metal interconnects; metal lines; metal wires; silicon dies; single 3DIC stack; through-silicon via; vertical integration; Capacitance; Couplings; Integrated circuit modeling; Metals; Solid modeling; Through-silicon vias; Wires; Coupling; Doping; Lumped Model; Metal; TSV; Three-Dimensional ICs; Through Silicon Via;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
DOI :
10.1109/ICECS.2012.6463647
