TSV stress-aware performance and reliability analysis

We analyze delay, dynamic and leakage power of TSV based 3D-ICs under stress-induced mobility and threshold voltage changes. It is shown that variations in MOS device characteristics can influence the overall chip performance depending on the number of affected devices. We also analyze the impact of these changes on the reliability of circuit designs. Mean time to failure (MTTF) is calculated under the influence of stress. We also discuss a technique to reduce the variation of device parameters by providing Keep-Out-Zone for selective TSVs and placing the critical cells around those TSVs.