Title :
An efficient solution space for floorplan of 3D-LSI
Author :
Tezuka, Hiroyuki ; Fujiyoshi, Kunihiro
Author_Institution :
Dept. of Electr. & Electron. Eng., Tokyo Univ. of Agric. & Technol., Tokyo, Japan
Abstract :
One of the methods to obtain good floorplans for 3D-LSI is, to search for good solutions by simulated annealing, a famous stochastic search algorithm, based on a representation of placement or rectangular dissection. Since we think that redundantly large variety of adjacent solutions for stochastic search degrades convergence of the searching, in this paper, we proposed Single-SP, which represents relative position of modules for each device layer by one sequence-pair and a sequence of numbers, and MOVE operations which have small variety of adjacent solutions. The effectiveness of the proposed representation and MOVE operations were confirmed by experimental comparisons.
Keywords :
integrated circuit layout; large scale integration; search problems; simulated annealing; three-dimensional integrated circuits; 3D-LSI floorplan; MOVE operations; device layer; placement representation; rectangular dissection; sequence pair; simulated annealing; single-SP; stochastic search algorithm; Benchmark testing; Convergence; Silicon; Simulated annealing; Stochastic processes; Through-silicon vias; Wires;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on
Conference_Location :
Seville
Print_ISBN :
978-1-4673-1261-5
Electronic_ISBN :
978-1-4673-1259-2
DOI :
10.1109/ICECS.2012.6463651
