Low-power two´s-complement multiplication based on selective activation

A low-power two´s-complement multiplier architecture is proposed in this paper. It is shown that by initially partitioning a multiplier into blocks, and selectively activating appropriate blocks depending on the input values, substantial power dissipation reduction is achieved for cases of practical interest. The proposed architecture is quantitatively evaluated in hardware, by mapping several instantiations of the proposed architecture onto a 90nm standard-cell library. Power savings in the order of 38% are achieved in comparison to typical multipliers. Furthermore, delay reduction is also achieved.