A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS

Author

Sherazi, M.Y. ; Nilsson, Per-Ake ; Sjoland, Henrik ; Rodrigues, Joachim Neves

Author_Institution

Dept. of Electr. & Inf. Technol., Lund Univ., Lund, Sweden

fYear

2012

fDate

9-12 Dec. 2012

Firstpage

448

Lastpage

451

Abstract

Measurements of a sub-threshold (sub-V_T) decimation filter, composed of four half band digital (HBD) filters in 65 nm CMOS are presented. Different unfolded architectures are analyzed and implemented to combat speed degradation. The architectures are analyzed for throughput and energy efficiency over several threshold options. Reliability in the sub-V_T domain is analyzed by Monte-Carlo simulations. The simulation results are validated by measurements and demonstrate that low-power standard threshold logic (LP-SVT) and different architectural flavours are suitable for a low-power implementation. Silicon measurements prove functionality down to 350mV supply, with a maximum clock frequency of 500 kHz, having an energy dissipation of 102 fJ/cycle.

Keywords

CMOS integrated circuits; Monte Carlo methods; digital filters; integrated circuit reliability; CMOS technology; LP-SVT; Monte Carlo simulations; decimation filter chain; energy efficiency; frequency 500 kHz; half band digital filters; low-power standard threshold logic; size 65 nm; speed degradation; subthreshold decimation filter; voltage 350 mV; Clocks; Current measurement; Delay; Energy dissipation; Energy measurement; FCC; Temperature measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems (ICECS), 2012 19th IEEE International Conference on

Conference_Location

Seville

Print_ISBN

978-1-4673-1261-5

Electronic_ISBN

978-1-4673-1259-2

Type

conf

DOI

10.1109/ICECS.2012.6463654

Filename

6463654