CBSC-based pipelined analog-to-digital converters: Power dissipation bound analysis

The comparator-based switched-capacitor (CBSC) technique has been used in low power analog-to-digital converters (ADCs). The objective of this paper is to derive the theoretical minimum power dissipation bound for CBSC-based pipelined ADCs with digital error correction of 1.5 bit/stage. To achieve this, the constituent building blocks whose performance is limited by noise, are examined. The optimum values of the design parameters influencing the power dissipation bound are also investigated including the optimal output ramp rates needed to achieve a given linearity constraint, comparator bias current and delay time. The derived equations are verified through behavioral simulation in MATLAB.