Decoder for an enhanced serial generalized bit flipping algorithm

An enhanced serial generalized bit-flipping algorithm is proposed in this paper. This new algorithm includes method to compute the extrinsic information during all the iterations, improving the performance of the algorithm in the waterfall region compared to the direct serial description. In addition, the algorithm allow us to reduce the storage resources the derived architecture. The decoder was implemented on a Virtex-VI FPGA device for the (837,723) non-binary code over GF(2⁵), achieving 439 Mbps at 10 iterations.