Channel mismatch background calibration for pipelined time interleaved ADCs

This paper presents a background calibration technique for channel mismatch errors in pipelined time interleaved ADCs. These mismatches include gain and offset mismatches for pipelined sub-ADC´s stages and the time skew error for each sub-ADC. The presented calibration technique is based on least mean-square adaptive filtering and requires an extra slow but accurate sub-ADC. The technique was implemented on an FPGA to evaluate its resource utilization. Simulation results demonstrate a 40 dB improvement in the measured SNR.